This invention relates to the calibration of memory circuits in a computer system. More particularly, this invention relates to the calibration of memory circuits to reduce spurious data during memory circuit accesses.
Computer systems that incorporate memory circuits are generally designed to ensure high accuracy of the memory circuits because faulty memory circuits lead to malfunctioning computer systems. A common obstacle to proper functioning of memory circuits is lengthy transitional delay between ones and zeroes, as well as clock skew in the case of clocked memories. Spurious data occurs when ones are read as zeroes, and vice-versa.
Memory circuits increasingly incorporate variable drive buffers to drive data onto external busses. These buffers may be programmed to drive different levels of current and voltage in order to, for example, accommodate varying environmental conditions such as bus loading and ambient temperature. The adjustability of memory circuit output parameters can be used to reduce the probability of spurious data. One metric of memory circuit data quality is based on the measured data eye pattern of the memory circuit. Thus, it may be desirable to calibrate memory circuit output parameters based on measurements of the observed data eye patterns of memory circuit outputs.